1. Field of the Invention
The present invention relates to a semiconductor circuit including multiple wires in which cross-talk occurs, a delay adjustment method therefor and a layout method therefor, and more particularly to a semiconductor Circuit aiming at suppressing a variation of delay time, a delay adjustment method therefor and a layout method therefor.
2. Description of the Related Art
The semiconductor circuit contains multiple signal lines disposed in parallel to each other and, for example, a device such as inverter and buffer are provided to them at a matching position in a signal propagation direction. FIG. 1 is a circuit diagram showing a structure of a conventional semiconductor circuit.
For example, two signal lines S11, S12 are disposed in parallel to each other. Buffers BU11 and BU13 are disposed on the signal line S11 in a signal propagation direction in this order. Then, buffers BU15 and BU14 are disposed on the signal line S12 in the signal propagation direction in this order. The buffers BU11 and BU15 are disposed at a position matching with each other in the signal propagation direction, namely, adjacent position. The buffers BU13 and BU14 are disposed at a position matching with each other in the signal propagation direction. Therefore, the length of wire between the buffers BU11 and BU13 is equal to the length of wire between the buffers BU15 and BU14.
A resistor having a resistance xe2x80x9cRxe2x80x9d parasitizes to each wire between the buffers BU11 and BU13, and between the buffers BU15 and BU14. Further, a capacitor having capacitance xe2x80x9cCxe2x80x9d parasitizes between wire between the buffers BU11 and BU13, and the wire between the buffers BU15 and BU14.
If a signal is inputted to the buffers BU11 and BU15 in the conventional semiconductor circuit having such a structure, the respective signals are driven by the buffers BU11 and BU15 and then inputted to the buffers BU13 and BU14. At this time, a delay occurs in signal propagation. If changing signals are inputted to both the signal lines S11 and S12, as compared to a case where a signal inputted to one signal line is not changed, the delay time is decreased by cross-talk if that input signal is in phase. If the input signal is in opposite phase, the delay is increased by the cross-talk.
An above-described variation of the delay time becomes more evident as the capacitance between the wires is increased. Therefore, there is provided a semiconductor circuit in which the capacitance between the wires is reduced by providing another buffer between the buffers. FIG. 2 is a circuit diagram showing a structure of a conventional semiconductor circuit intended to reduce the capacitance between the wires.
In the conventional semiconductor circuit intended to reduce capacitance between the wires, a buffer BU12 is connected between the buffers BU11 and BU13 and a buffer BU16 is connected between the buffers BU15 and BU14.
Next, an operation of the conventional semiconductor circuit having the above-described structure will be described. FIGS. 3A-3D are diagrams showing an operation of the conventional semiconductor circuit shown in FIG. 2. FIG. 3A is a circuit diagram showing an operation when input signals rise on both the signal lines S11 and S12. FIG. 3B is a circuit diagram showing an operation when a input signal rises on the signal line S11 while a signal falls on the signal S12. FIG. 3C is a circuit diagram showing an operation when the input signal falls on the signal line S11 while the signal rises on the signal line S12. FIG. 3D is a circuit diagram showing an operation when the input signals fall on both the signal lines S11, S12.
If both the signals propagated through the signal lines S11 and S12 rise, the signals propagated through the signal lines S11 and S12 are outputted from the buffers B11 and BU15 in non-inverted state as shown in FIG. 3A. Because these output signals are in phase with each other, a delay time until they are inputted to the buffers BU12 and BU16 is decreased by cross-talk as compared to a case where the mating signal is not changed.
After that both the signals are outputted from the buffers BU12 and BU16 in non-inverted state. Because these output signals are in phase, the delay time until they are inputted to the buffers BU13 and BU14 is further decreased by the cross-talk as compared to a case where the mating signal is not changed.
On the other hand, if a signal propagated through the signal line S11 rises while a signal propagated through the signal line S12 falls, signals propagated through the signal lines S11 and S12 are outputted from the buffers BU11 and BU15 in non-inverted state. Because these signals are in opposite phase, the delay time until they are inputted to the buffers BU12 and BU16 is increased by cross-talk as compared to a case where the mating signal is not changed.
After that, both the signals are outputted from the buffers BU12 and BU16 in non-inverted state. Because these output signals are in opposite phase, the delay time until they are inputted to the buffers BU13 and BU14 is further increased by the cross-talk as compared to a case where the mating signal is not changed.
If a signal propagated through the signal line S11 falls while a signal propagated through the Signal line S12 rises, the signals are changed in opposite phase to FIG. 3B as shown in FIG. 3C. If both signals propagated through the signal lines S11 and S12 fall, the signals are changed in opposite phase to FIG. 3A as shown in FIG. 3D.
By providing with the buffers BU12, BU16 in the conventional semiconductor circuit shown in FIG. 2, the driving performance is raised and the capacitance between wires is reduced so as to suppress a variation due to cross-talk.
To remove a timing shift generated by cross-talk between signals propagated through the adjacent two signal lines, such a semiconductor circuit having inverters to accelerate or retard propagation of signals has been proposed (Japanese Patent Application Laid-Open No. 8-330934).
However, in the conventional semiconductor circuit shown in FIG. 2, the delay time of a signal in phase is only decreased while the delay of a signal in opposite phase is only decreased because the buffers BU12 and BU16 added to the circuit shown in FIG. 1 are of positive logic. Thus, it is necessary to provide with a multiplicity of buffers to suppress the variation of the delay time. As a result, there exists a problem that production cost is increased or the delay is increased due to a switching delay of a buffer.
Although in the conventional semiconductor circuit proposed in Japanese Patent Application Laid-Open No. 8-330934, a generated timing shift can be reduced, there is such a problem that if a signal having no timing shift is inputted, the signal propagation is forced to be accelerated or retarded.
The object of the present invention is to provide a semiconductor circuit capable of preventing a variation of the delay time caused by cross-talk, a delay adjustment method therefor and a layout method therefor.
According to one aspect of the present invention, a semiconductor circuit comprises first and second wires disposed adjacent to each other, and even pairs of buffers and inverters. A buffer and an inverter in each of the pairs are disposed on the first or second wires respectively. The first and second wires are respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. Lengths of the wire sections are equal to each other between adjacent wire sections of the first and second wires. Gaps between the first and second wires are equal to each other between each two wire sections from the input side of the first and second wires.
According to another aspect of the present invention, a semiconductor circuit comprises first and second wires disposed adjacent to each other, and even pairs of buffers and inverters. A buffer and an inverter in each of the pairs are disposed on the first or second wires respectively. The first and second wires are respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. Resistances of the wire sections are equal to each other between adjacent wire sections of the first and second wires. Capacitance between the first and second wires are equal to each other between each two wire sections from the input side of the first and second wires.
According to another aspect of the present invention, a delay adjustment method for semiconductor circuit is a method for a semiconductor circuit comprising first and second wires disposed adjacent to each other, and even pairs of buffers and inverters, a buffer and an inverter in each of the pairs being disposed on the first or second wires respectively, and the first and second wires being respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. The method comprises the steps of setting lengths of the wire sections equal to each other between adjacent wire sections of the first and second wires, and setting gaps between first and second wires equal to each other between each two wire sections from the input side of the first and second wires.
According to another aspect of the present invention, a delay adjustment method for semiconductor circuit is a method for a semiconductor circuit comprising first and second wires disposed adjacent to each other, and even pairs of buffers and inverters, a buffer and an inverter in each of the pairs being disposed on the first or second wires respectively, and the first and second wires being respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. The method comprises the steps of setting resistances of the wire sections equal to each other between adjacent wire sections of the first and second wires, and setting capacitance between first and second wires equal to each other between each two wire sections from the input side of the first and second wires.
According to another aspect of the present invention, a layout method for semiconductor circuit is a method for a semiconductor circuit comprising first and second wires disposed adjacent to each other, and even pairs of buffers and inverters, a buffer and an inverter in each of the pairs being disposed on the first or second wires respectively, and the first and second wires being respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. The method comprises the steps of setting lengths of the wire sections equal to each other between adjacent wire sections of the first and second wires, and setting gaps between first and second wires equal to each other between each two wire sections from the input side of the first and second wires.
According to another aspect of the present invention, a layout method for semiconductor circuit is a method for a semiconductor circuit comprising first and second wires disposed adjacent to each other, and even pairs of buffers and inverters, a buffer and an inverter in each of the pairs being disposed on the first or second wires respectively, and the first and second wires being respectively divided to even wire sections by the even pairs and a device or terminal connected to the output side of the pairs. The method comprises the steps of setting resistances of the wire sections equal to each other between adjacent wire sections of the first and second wires, and setting capacitance between first and second wires equal to each other between each two wire sections from the input side of the first and second wires.
According to these aspects of the present invention, if an output signal propagated through one wire rises while an output signal propagated through the other wire falls by the first pair of buffer and inverter, the delay time is increased by cross-talk. However, by the second pair of the buffer and inverter, the both output signals rise or fall uniformly. Therefore, the delay time is decreased by cross-talk. Because an absolute value of an increase of the delay time is equal to that of a decrease thereof, a variation of the delay time, which conventionally occurs in a signal outputted from continuous even wire sections, can be prevented. On the other hand, if output signals propagated through both the wires rise or fall uniformly by the first pair of the buffer and inverter, the delay time is decreased by cross-talk. However, one of the aforementioned output signals rises while the other one falls by the second pair of the buffer and inverter, so that the delay time is increased by cross-talk. Therefore, in this case also, the variation of the delay time, which conventionally occurs in a signal outputted from continuous even wire sections, can be prevented. That is, in any case, the increase and decrease of the delay time are killed by each other throughout the continuous even wire sections. Consequently, an entire variation of the delay time can be prevented, so that adjustment of signal timing can be carried out easily.